Vertically Stacked and Self-Encapsulated van der Waals Heterojunction Diodes Using Two-Dimensional Layered Semiconductors

  • Jinshui Miao
  • , Zhihao Xu
  • , Qing Li
  • , Arthur Bowman
  • , Suoming Zhang
  • , Weida Hu
  • , Zhixian Zhou
  • , Chuan Wang

Research output: Contribution to journalArticlepeer-review

66 Scopus citations

Abstract

van der Waals heterojunctions using 2D semiconducting materials could overcome the defect issues included by lattice mismatch in conventional epitaxially grown heterojunctions with bulk materials and could enable a much wider palette for choice of materials and more sophisticated device design. Such 2D heterojunction devices are of great interest for important functional devices such as diodes, bipolar junction transistors, light-emitting diodes, and photodetectors. In this paper, we demonstrate a truly vertical p-n heterojunction diode built from 2D semiconductors (MoS2 and BP) and compare its performance against conventional lateral 2D heterojunction devices (partially overlapped 2D heterostructures). Both vertical and lateral p-n heterostructure diodes exhibit a strong rectification ratio even with no gate voltage applied. More importantly, the results show that the vertical diode delivers 70 times higher current density under forward bias than a conventional lateral device design and the improved device performance can be attributed to the complete elimination of series resistance. Low-temperature measurements and TCAD simulations are used to determine the barrier height at the junctions. Moreover, the vertical device structure allows certain ambiently unstable 2D semiconductors to be fully encapsulated by the materials on top, preventing the material from degradation. This work demonstrates the potential of using the vertically stacked 2D semiconductors for future nanoelectronic and optoelectronic devices with optimal performance.

Original languageEnglish
Pages (from-to)10472-10479
Number of pages8
JournalACS nano
Volume11
Issue number10
DOIs
StatePublished - Oct 24 2017

Keywords

  • 2D semiconductor
  • encapsulation
  • heterostructure
  • p-n junction diode
  • vertical

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