Toward Evaluating High-Level Synthesis Portability and Performance between Intel and Xilinx FPGAs

Anthony M. Cabrera, Aaron R. Young, Jacob Lambert, Zhili Xiao, Amy An, Seyong Lee, Zheming Jin, Jungwon Kim, Jeremy Buhler, Roger D. Chamberlain, Jeffrey S. Vetter

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

Offloading computation from a CPU to a hardware accelerator is becoming a more common solution for improving performance because traditional gains enabled by Moore's law and Dennard scaling have slowed. GPUs are often used as hardware accelerators, but field-programmable gate arrays (FPGAs) are gaining traction. FPGAs are beneficial because they allow hardware specific to a particular application to be created. However, they are notoriously difficult to program. To this end, two of the main FPGA manufacturers, Intel and Xilinx, have created tools and frameworks that enable the use of higher level languages to design FPGA hardware. Although Xilinx kernels can be designed by using C/C++, both Intel and Xilinx support the use of OpenCL C to architect FPGA hardware. However, not much is known about the portability and performance between these two device families other than the fact that it is theoretically possible to synthesize a kernel meant for Intel to Xilinx and vice versa. In this work, we evaluate the portability and performance of Intel and Xilinx kernels. We use OpenCL C implementations of a subset of the Rodinia benchmarking suite that were designed for an Intel FPGA and make the necessary modifications to create synthesizable OpenCL C kernels for a Xilinx FPGA. We find that the difficulty of porting certain kernel optimizations varies, depending on the construct. Once the minimum amount of modifications is made to create synthesizable hardware for the Xilinx platform, more nontrivial work is needed to improve performance. However, we find that constructs that are known to be performant for an FPGA should improve performance regardless of the platform; the difficulty comes in deciding how to invoke certain kernel optimizations while also abiding by the constraints enforced by a given platform's hardware compiler.

Original languageEnglish
Title of host publicationInternational Workshop on OpenCL, IWOCL 2021
PublisherAssociation for Computing Machinery
ISBN (Electronic)9781450390330
DOIs
StatePublished - Apr 27 2021
Event2021 International Workshop on OpenCL, IWOCL 2021 - Virtual, Online, Germany
Duration: Apr 27 2021Apr 29 2021

Publication series

NameACM International Conference Proceeding Series

Conference

Conference2021 International Workshop on OpenCL, IWOCL 2021
Country/TerritoryGermany
CityVirtual, Online
Period04/27/2104/29/21

Keywords

  • FPGA
  • hardware accelerator
  • high level synthesis
  • performance
  • portability
  • Rodinia
  • Xilinx

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