TY - JOUR

T1 - Synthesis of bias-scalable CMOS analog computational circuits using margin propagation

AU - Gu, Ming

AU - Chakrabartty, Shantanu

N1 - Funding Information:
Manuscript received February 24, 2011; revised May 31, 2011; accepted July 08, 2011. Date of publication September 19, 2011; date of current version January 27, 2012. This work was supported by the National Science Foundation (NSF) under Grant CCF:0728996. This paper was recommended by Associate Editor V. Gaudet.

PY - 2012

Y1 - 2012

N2 - Approximation techniques are useful for implementing pattern recognizers, communication decoders and sensory processing algorithms where computational precision is not critical to achieve the desired system level performance. In our previous work, we had proposed margin propagation (MP) as an efficient piecewise linear (PWL) approximation technique to a log-sum-exp function and had demonstrated its advantages for implementing probabilistic decoders. In this paper, we present a systematic and a generalized approach for synthesizing analog piecewise-linear (PWL) computing circuits using the MP principle. MP circuits use only addition, subtraction and threshold operations and hence can be implemented using universal conservation principles like the Kirchoff's current law. Thus, unlike the conventional translinear CMOS current-mode circuits, the operation of the MP circuits are functionally similar in weak, moderate, and strong inversion regimes of the MOS transistor making the design approach bias-scalable. This paper presents measured results from MP circuits prototyped in a 0.5 μm standard CMOS process verifying the bias-scalable property. As an example, we apply the synthesis approach towards designing linear classifiers and we verify its performance using measured results.

AB - Approximation techniques are useful for implementing pattern recognizers, communication decoders and sensory processing algorithms where computational precision is not critical to achieve the desired system level performance. In our previous work, we had proposed margin propagation (MP) as an efficient piecewise linear (PWL) approximation technique to a log-sum-exp function and had demonstrated its advantages for implementing probabilistic decoders. In this paper, we present a systematic and a generalized approach for synthesizing analog piecewise-linear (PWL) computing circuits using the MP principle. MP circuits use only addition, subtraction and threshold operations and hence can be implemented using universal conservation principles like the Kirchoff's current law. Thus, unlike the conventional translinear CMOS current-mode circuits, the operation of the MP circuits are functionally similar in weak, moderate, and strong inversion regimes of the MOS transistor making the design approach bias-scalable. This paper presents measured results from MP circuits prototyped in a 0.5 μm standard CMOS process verifying the bias-scalable property. As an example, we apply the synthesis approach towards designing linear classifiers and we verify its performance using measured results.

KW - Analog computation

KW - current-mode circuits

KW - margin propagation (MP)

KW - moderate-inversion circuits

KW - piecewise-linear (PWL) circuit

KW - translinear

UR - http://www.scopus.com/inward/record.url?scp=84856487714&partnerID=8YFLogxK

U2 - 10.1109/TCSI.2011.2163968

DO - 10.1109/TCSI.2011.2163968

M3 - Article

AN - SCOPUS:84856487714

SN - 1549-8328

VL - 59

SP - 243

EP - 254

JO - IEEE Transactions on Circuits and Systems I: Regular Papers

JF - IEEE Transactions on Circuits and Systems I: Regular Papers

IS - 2

M1 - 6021350

ER -