Supporting Mixed Real-Time Workloads in Multithreaded Processors with Segmented Instruction Caches

This chapter proposes the use of segmented instruction caches along with profile-driven code scheduling to provide flexible instruction delivery to real-time and nonreal-time threads running on the same multithreaded processor. This technique is particularly useful in network processors (NP) data processors, which are multithreaded yet inhibited by a fixed-size control store. The segmented instruction cache allows real-time programs to map into a private segment large enough to avoid misses while allowing nonreal-time programs to suffer misses, keeping all cache conflicts limited within individual segments. This removes program size restrictions on nonreal-time code without sacrificing guaranteed instruction delivery to real-time programs. Profiling is also used to explore a variety of program-specific segment sizing strategies. The proposed design is evaluated on a selection of programs running on both direct-mapped and set-associative segmented instruction caches. Several program-specific segment sizing strategies are evaluated. Code scheduling is an effective method for removing majority of the conflict misses, often reducing miss rates on a selection of programs by a range of 10 percent to 60 percent.