Sub-microwatt analog VLSI support vector machine for pattern classification and sequence estimation

Shantanu Chakrabartty; Gert Cauwenberghs

Sub-microwatt analog VLSI support vector machine for pattern classification and sequence estimation

Shantanu Chakrabartty, Gert Cauwenberghs

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

An analog system-on-chip for kernel-based pattern classification and sequence estimation is presented. State transition probabilities conditioned on input data are generated by an integrated support vector machine. Dot product based kernels and support vector coefficients are implemented in analog programmable floating gate translinear circuits, and probabilities are propagated and normalized using sub-threshold current-mode circuits. A 14-input, 24-state, and 720-support vector forward decoding kernel machine is integrated on a 3mm×3mm chip in 0.5μm CMOS technology. Experiments with the processor trained for speaker verification and phoneme sequence estimation demonstrate real-time recognition accuracy at par with floating-point software, at sub-microwatt power.

Original language	English
Title of host publication	Advances in Neural Information Processing Systems 17 - Proceedings of the 2004 Conference, NIPS 2004
Publisher	Neural information processing systems foundation
ISBN (Print)	0262195348, 9780262195348
State	Published - 2005
Event	18th Annual Conference on Neural Information Processing Systems, NIPS 2004 - Vancouver, BC, Canada Duration: Dec 13 2004 → Dec 16 2004

Publication series

Name	Advances in Neural Information Processing Systems
ISSN (Print)	1049-5258

Conference

Conference	18th Annual Conference on Neural Information Processing Systems, NIPS 2004
Country/Territory	Canada
City	Vancouver, BC
Period	12/13/04 → 12/16/04

Cite this

@inproceedings{7d0339e996a049dbbc847878ce9ad330,

title = "Sub-microwatt analog VLSI support vector machine for pattern classification and sequence estimation",

abstract = "An analog system-on-chip for kernel-based pattern classification and sequence estimation is presented. State transition probabilities conditioned on input data are generated by an integrated support vector machine. Dot product based kernels and support vector coefficients are implemented in analog programmable floating gate translinear circuits, and probabilities are propagated and normalized using sub-threshold current-mode circuits. A 14-input, 24-state, and 720-support vector forward decoding kernel machine is integrated on a 3mm×3mm chip in 0.5μm CMOS technology. Experiments with the processor trained for speaker verification and phoneme sequence estimation demonstrate real-time recognition accuracy at par with floating-point software, at sub-microwatt power.",

author = "Shantanu Chakrabartty and Gert Cauwenberghs",

year = "2005",

language = "English",

isbn = "0262195348",

series = "Advances in Neural Information Processing Systems",

publisher = "Neural information processing systems foundation",

booktitle = "Advances in Neural Information Processing Systems 17 - Proceedings of the 2004 Conference, NIPS 2004",

note = "18th Annual Conference on Neural Information Processing Systems, NIPS 2004 ; Conference date: 13-12-2004 Through 16-12-2004",

}

Chakrabartty, S & Cauwenberghs, G 2005, Sub-microwatt analog VLSI support vector machine for pattern classification and sequence estimation. in Advances in Neural Information Processing Systems 17 - Proceedings of the 2004 Conference, NIPS 2004. Advances in Neural Information Processing Systems, Neural information processing systems foundation, 18th Annual Conference on Neural Information Processing Systems, NIPS 2004, Vancouver, BC, Canada, 12/13/04.

Sub-microwatt analog VLSI support vector machine for pattern classification and sequence estimation. / Chakrabartty, Shantanu; Cauwenberghs, Gert.
Advances in Neural Information Processing Systems 17 - Proceedings of the 2004 Conference, NIPS 2004. Neural information processing systems foundation, 2005. (Advances in Neural Information Processing Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Sub-microwatt analog VLSI support vector machine for pattern classification and sequence estimation

AU - Chakrabartty, Shantanu

AU - Cauwenberghs, Gert

PY - 2005

Y1 - 2005

N2 - An analog system-on-chip for kernel-based pattern classification and sequence estimation is presented. State transition probabilities conditioned on input data are generated by an integrated support vector machine. Dot product based kernels and support vector coefficients are implemented in analog programmable floating gate translinear circuits, and probabilities are propagated and normalized using sub-threshold current-mode circuits. A 14-input, 24-state, and 720-support vector forward decoding kernel machine is integrated on a 3mm×3mm chip in 0.5μm CMOS technology. Experiments with the processor trained for speaker verification and phoneme sequence estimation demonstrate real-time recognition accuracy at par with floating-point software, at sub-microwatt power.

AB - An analog system-on-chip for kernel-based pattern classification and sequence estimation is presented. State transition probabilities conditioned on input data are generated by an integrated support vector machine. Dot product based kernels and support vector coefficients are implemented in analog programmable floating gate translinear circuits, and probabilities are propagated and normalized using sub-threshold current-mode circuits. A 14-input, 24-state, and 720-support vector forward decoding kernel machine is integrated on a 3mm×3mm chip in 0.5μm CMOS technology. Experiments with the processor trained for speaker verification and phoneme sequence estimation demonstrate real-time recognition accuracy at par with floating-point software, at sub-microwatt power.

UR - http://www.scopus.com/inward/record.url?scp=84898993017&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:84898993017

SN - 0262195348

SN - 9780262195348

T3 - Advances in Neural Information Processing Systems

BT - Advances in Neural Information Processing Systems 17 - Proceedings of the 2004 Conference, NIPS 2004

PB - Neural information processing systems foundation

T2 - 18th Annual Conference on Neural Information Processing Systems, NIPS 2004

Y2 - 13 December 2004 through 16 December 2004

ER -

Sub-microwatt analog VLSI support vector machine for pattern classification and sequence estimation

Abstract

Publication series

Conference

Other files and links

Fingerprint

Cite this