Study and implementation of an embedded flash CISC/DSP microprocessor

A new architecture of an embedded Flash CISC/DSP microprocessor is presented. Under unified enhanced complex instruction set. The single core processor has been implemented by using RISC and pipeline design principles based on Harvard and register-to-register architecture. To achieve double functionality of DSP and general CPU, we have combined general CPU, embedded FLASH, instruction buffer and DSP functional units, such as single clock MAC, barrel shifter, fast loop processing unit, etc. in a single architecture. This processor is fabricated using 0.35 μm CMOS process, and the power consumption of the chip is less than 425 mW working under 3.3 V voltage and 80 MHz clock. The low-cost high performance microprocessor is well suited for a wide range of SOC applications.