TY - JOUR
T1 - Silicon support vector machine with on-line learning
AU - Genov, Roman
AU - Chakrabartty, Shantanu
AU - Cauwenberghs, Gert
N1 - Funding Information:
This research was supported by NSERC Discovery 261606-03, NSF IIS-0209289, ONR/DARPA N00014-00-C-0315, ONR N00014-99-1-0612, the Catalyst Foundation, and WatchVision Corporation. The chip was fabricated through the MOSIS service.
PY - 2003/5
Y1 - 2003/5
N2 - Training of support vector machines (SVMs) amounts to solving a quadratic programming problem over the training data. We present a simple on-line SVM training algorithm of complexity approximately linear in the number of training vectors, and linear in the number of support vectors. The algorithm implements an on-line variant of sequential minimum optimization (SMO) that avoids the need for adjusting select pairs of training coefficients by adjusting the bias term along with the coefficient of the currently presented training vector. The coefficient assignment is a function of the margin returned by the SVM classifier prior to assignment, subject to inequality constraints. The training scheme lends efficiently to dedicated SVM hardware for real-time pattern recognition, implemented using resources already provided for run-time operation. Performance gains are illustrated using the Kerneltron, a massively parallel mixed-signal VLSI processor for kernel-based real-time video recognition.
AB - Training of support vector machines (SVMs) amounts to solving a quadratic programming problem over the training data. We present a simple on-line SVM training algorithm of complexity approximately linear in the number of training vectors, and linear in the number of support vectors. The algorithm implements an on-line variant of sequential minimum optimization (SMO) that avoids the need for adjusting select pairs of training coefficients by adjusting the bias term along with the coefficient of the currently presented training vector. The coefficient assignment is a function of the margin returned by the SVM classifier prior to assignment, subject to inequality constraints. The training scheme lends efficiently to dedicated SVM hardware for real-time pattern recognition, implemented using resources already provided for run-time operation. Performance gains are illustrated using the Kerneltron, a massively parallel mixed-signal VLSI processor for kernel-based real-time video recognition.
KW - Analog array processors
KW - Kernel machines
KW - Large margin classifiers
KW - Matrix-vector multiplication (MVM)
KW - Pattern recognition
KW - Quadratic programming (QP)
KW - Sequential minimum optimization (SMO)
KW - Support vector machine (SVM)
UR - http://www.scopus.com/inward/record.url?scp=0038266787&partnerID=8YFLogxK
U2 - 10.1142/S0218001403002472
DO - 10.1142/S0218001403002472
M3 - Article
AN - SCOPUS:0038266787
SN - 0218-0014
VL - 17
SP - 385
EP - 404
JO - International Journal of Pattern Recognition and Artificial Intelligence
JF - International Journal of Pattern Recognition and Artificial Intelligence
IS - 3
ER -