TY - GEN
T1 - Scavenging thermal-noise energy for implementing long-term self-powered CMOS timers
AU - Zhou, Liang
AU - Sarkar, Pikul
AU - Chakrabartty, Shantanu
PY - 2013
Y1 - 2013
N2 - One of the major challenges in remotely powered sensors is that events being monitored can not be time-stamped due to the unavailability of a continuously active timer or system clock. Implementing such a timer would require access to a perennial source of energy, which for a structural health monitoring (SHM) application, could easily span several years. In this paper, we present a novel approach to implement self-powered timers that only requires presence of ambient thermal energy. The operational principle of the timer is based on the physics of trap-assisted electron transportation in floating-gate capacitors which yields leakage currents down to 10-21A. Using a differential architecture the proposed timer compensates for the effects of temperature variations during the timer read-out. In this paper we validate the proof-of-concept using measurement results obtained from different timer topologies which have been prototyped in a 0.5μm CMOS process.
AB - One of the major challenges in remotely powered sensors is that events being monitored can not be time-stamped due to the unavailability of a continuously active timer or system clock. Implementing such a timer would require access to a perennial source of energy, which for a structural health monitoring (SHM) application, could easily span several years. In this paper, we present a novel approach to implement self-powered timers that only requires presence of ambient thermal energy. The operational principle of the timer is based on the physics of trap-assisted electron transportation in floating-gate capacitors which yields leakage currents down to 10-21A. Using a differential architecture the proposed timer compensates for the effects of temperature variations during the timer read-out. In this paper we validate the proof-of-concept using measurement results obtained from different timer topologies which have been prototyped in a 0.5μm CMOS process.
UR - http://www.scopus.com/inward/record.url?scp=84883411333&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2013.6572313
DO - 10.1109/ISCAS.2013.6572313
M3 - Conference contribution
AN - SCOPUS:84883411333
SN - 9781467357609
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 2203
EP - 2206
BT - 2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
T2 - 2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
Y2 - 19 May 2013 through 23 May 2013
ER -