TY - JOUR
T1 - Performance predictions for speculative, synchronous, VLSI logic simulation
AU - Noble, Bradley L.
AU - Wade, J. Cris
AU - Chamberlain, Roger D.
PY - 2001
Y1 - 2001
N2 - VLSI logic simulation is an application area in which execution time improvements can have direct economic benefits. Here, we investigate the use of parallel simulation techniques to improve the performance of VLSI logic simulation, including the often neglected issue of sensitivity to variations in the simulation workload. Performance predictions are presented for the use of speculative computation in synchronous discrete-event simulation of VLSI systems.
AB - VLSI logic simulation is an application area in which execution time improvements can have direct economic benefits. Here, we investigate the use of parallel simulation techniques to improve the performance of VLSI logic simulation, including the often neglected issue of sensitivity to variations in the simulation workload. Performance predictions are presented for the use of speculative computation in synchronous discrete-event simulation of VLSI systems.
UR - https://www.scopus.com/pages/publications/0035009845
U2 - 10.1109/SIMSYM.2001.922115
DO - 10.1109/SIMSYM.2001.922115
M3 - Article
AN - SCOPUS:0035009845
SN - 0272-4715
SP - 56
EP - 64
JO - Proceedings of the IEEE Annual Simulation Symposium
JF - Proceedings of the IEEE Annual Simulation Symposium
ER -