Multiplierless MP-Kernel Machine for Energy-Efficient Edge Devices

We present a novel framework for designing multiplierless kernel machines that can be used on resource-constrained platforms such as intelligent edge devices. The framework uses a piecewise linear (PWL) approximation based on a margin propagation (MP) technique and uses only addition/subtraction, shift, comparison, and register underflow/overflow operations. We propose a hardware-friendly MP-based inference and online training algorithm that has been optimized for a field-programmable gate array (FPGA) platform. Our FPGA implementation eliminates the need for digital signal processor (DSP) units and reduces the number of Look-Up Tables (LUTs). By reusing the same hardware for inference and training, we show that the platform can overcome classification errors and local minima artifacts that result from MP approximation. The implementation of this proposed multiplierless MP-kernel machine on FPGA results in an estimated energy consumption of 13.4 pJ and power consumption of 107 mW with 9 k LUTs and Flip Flops (FFs) each for a 256 × 32 sized kernel making it superior in terms of power, performance, and area compared with other comparable implementations.