TY - JOUR
T1 - Multiplierless MP-Kernel Machine for Energy-Efficient Edge Devices
AU - Nair, Abhishek Ramdas
AU - Nath, Pallab Kumar
AU - Chakrabartty, Shantanu
AU - Thakur, Chetan Singh
N1 - Publisher Copyright:
© 1993-2012 IEEE.
PY - 2022/11/1
Y1 - 2022/11/1
N2 - We present a novel framework for designing multiplierless kernel machines that can be used on resource-constrained platforms such as intelligent edge devices. The framework uses a piecewise linear (PWL) approximation based on a margin propagation (MP) technique and uses only addition/subtraction, shift, comparison, and register underflow/overflow operations. We propose a hardware-friendly MP-based inference and online training algorithm that has been optimized for a field-programmable gate array (FPGA) platform. Our FPGA implementation eliminates the need for digital signal processor (DSP) units and reduces the number of Look-Up Tables (LUTs). By reusing the same hardware for inference and training, we show that the platform can overcome classification errors and local minima artifacts that result from MP approximation. The implementation of this proposed multiplierless MP-kernel machine on FPGA results in an estimated energy consumption of 13.4 pJ and power consumption of 107 mW with 9 k LUTs and Flip Flops (FFs) each for a 256 × 32 sized kernel making it superior in terms of power, performance, and area compared with other comparable implementations.
AB - We present a novel framework for designing multiplierless kernel machines that can be used on resource-constrained platforms such as intelligent edge devices. The framework uses a piecewise linear (PWL) approximation based on a margin propagation (MP) technique and uses only addition/subtraction, shift, comparison, and register underflow/overflow operations. We propose a hardware-friendly MP-based inference and online training algorithm that has been optimized for a field-programmable gate array (FPGA) platform. Our FPGA implementation eliminates the need for digital signal processor (DSP) units and reduces the number of Look-Up Tables (LUTs). By reusing the same hardware for inference and training, we show that the platform can overcome classification errors and local minima artifacts that result from MP approximation. The implementation of this proposed multiplierless MP-kernel machine on FPGA results in an estimated energy consumption of 13.4 pJ and power consumption of 107 mW with 9 k LUTs and Flip Flops (FFs) each for a 256 × 32 sized kernel making it superior in terms of power, performance, and area compared with other comparable implementations.
KW - Field-programmable gate array (FPGA)
KW - kernel machines
KW - margin propagation (MP)
KW - online learning
KW - support vector machines (SVMs)
UR - http://www.scopus.com/inward/record.url?scp=85135222032&partnerID=8YFLogxK
U2 - 10.1109/TVLSI.2022.3189780
DO - 10.1109/TVLSI.2022.3189780
M3 - Article
AN - SCOPUS:85135222032
SN - 1063-8210
VL - 30
SP - 1601
EP - 1614
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 11
ER -