MarginCiM: A 1.22 PetaOps/W, 2.5GS/s, 2.5pJ/correlation Margin-Processing Compute-in-Memory Array for RF to Feature Conversion

This paper presents a flexible, wideband RF/analog-to-feature conversion IC that performs concurrent dot products of quadrature signals with stored digital template vectors using a novel margin-processing (MP) cell co-integrated with SRAM, enabling analog/RF compute-in-memory (MarginCiM). By eliminating ADC conversion and leveraging compact current-thresholding MP cells, the approach simultaneously achieves both high energy efficiency and area efficiency for scalable feature detection. A 65nm CMOS implementation supports concurrent dot products of up to 512 I and Q samples (supporting sample rates from 40MS/s to 2.5GS/s) with 64 2-bit or 32 4-bit templates, each of length 512 (64 kb of total template SRAM memory). The analog compute array achieves order-of-magnitude higher correlator energy-efficiency (2.5pJ per correlation) compared to prior analog compute, up to 0.9TOPS throughput, and simultaneously achieves 1225.8TOPS/W energy efficiency for 2-bit operation and delivers 1.05TOPS/mm² area efficiency. Measurements confirm operation across 0.6V to 1.2V supply without requiring large capacitor arrays or explicit DACs. The MarginCiM array is combined with a wideband receiver to demonstrate analog and RF signal processing across code-domain synchronization, pilot detection, and modulation.