Low-latency and low-overhead encoder ASIC in the ATLAS LAr calorimeter trigger upgrade

Binwei Deng; Xiaoting Li; Datao Gong; Suen Hou; Chonghan Liu; Tiankuan Liu; Ping Kun Teng; Annie C. Xiang; Jingbo Ye; Xiandong Zhao

doi:10.1080/00207217.2016.1218059

Low-latency and low-overhead encoder ASIC in the ATLAS LAr calorimeter trigger upgrade

Binwei Deng
, Xiaoting Li
, Datao Gong
, Suen Hou
, Chonghan Liu
, Tiankuan Liu
, Ping Kun Teng
, Annie C. Xiang
, Jingbo Ye
, Xiandong Zhao

Division of Medical Physics

Research output: Contribution to journal › Article › peer-review

Abstract

In this article, an encoder Application Specific Integrated Circuit (ASIC) for high-speed serial data transmission is presented. The ASIC implements a low-latency and low-overhead line code and is fabricated with a commercial 0.25-µm Silicon-on-Sapphire CMOS technology. The ASIC operates at 640 MHz with a latency of no greater than 6.25 ns and the overhead of 14.3%. The encoder will be integrated with a serialiser and will be used in the A Toroidal LHC ApparatuS Liquid Argon (LAr) calorimeter Phase-I trigger upgrade.

Original language	English
Pages (from-to)	394-403
Number of pages	10
Journal	International Journal of Electronics
Volume	104
Issue number	3
DOIs	https://doi.org/10.1080/00207217.2016.1218059
State	Published - Mar 4 2017

Keywords

digital electronic circuits
Front-end electronics for detector readout
high-speed
low-latency
low-overhead
trigger concepts and systems (hardware and software)

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10.1080/00207217.2016.1218059

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title = "Low-latency and low-overhead encoder ASIC in the ATLAS LAr calorimeter trigger upgrade",

abstract = "In this article, an encoder Application Specific Integrated Circuit (ASIC) for high-speed serial data transmission is presented. The ASIC implements a low-latency and low-overhead line code and is fabricated with a commercial 0.25-µm Silicon-on-Sapphire CMOS technology. The ASIC operates at 640 MHz with a latency of no greater than 6.25 ns and the overhead of 14.3\%. The encoder will be integrated with a serialiser and will be used in the A Toroidal LHC ApparatuS Liquid Argon (LAr) calorimeter Phase-I trigger upgrade.",

keywords = "digital electronic circuits, Front-end electronics for detector readout, high-speed, low-latency, low-overhead, trigger concepts and systems (hardware and software)",

author = "Binwei Deng and Xiaoting Li and Datao Gong and Suen Hou and Chonghan Liu and Tiankuan Liu and Teng, \{Ping Kun\} and Xiang, \{Annie C.\} and Jingbo Ye and Xiandong Zhao",

note = "Funding Information: This work is supported by US-ATLAS R\&D program for the upgrade of the LHC, the US Department of Energy Grant [DE-FG02-04ER1299], National Science Council of Taiwan, Hubei Polytechnic University Key Research Project [16xjz04A] and Hubei Provincial Natural Science Foundation of China [Grant number 2014CFC1093]. Publisher Copyright: {\textcopyright} 2016 Informa UK Limited, trading as Taylor \& Francis Group.",

year = "2017",

month = mar,

day = "4",

doi = "10.1080/00207217.2016.1218059",

language = "English",

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journal = "International Journal of Electronics",

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AU - Deng, Binwei

AU - Li, Xiaoting

AU - Gong, Datao

AU - Hou, Suen

AU - Liu, Chonghan

AU - Liu, Tiankuan

AU - Teng, Ping Kun

AU - Xiang, Annie C.

AU - Ye, Jingbo

AU - Zhao, Xiandong

N1 - Funding Information: This work is supported by US-ATLAS R&D program for the upgrade of the LHC, the US Department of Energy Grant [DE-FG02-04ER1299], National Science Council of Taiwan, Hubei Polytechnic University Key Research Project [16xjz04A] and Hubei Provincial Natural Science Foundation of China [Grant number 2014CFC1093]. Publisher Copyright: © 2016 Informa UK Limited, trading as Taylor & Francis Group.

PY - 2017/3/4

Y1 - 2017/3/4

N2 - In this article, an encoder Application Specific Integrated Circuit (ASIC) for high-speed serial data transmission is presented. The ASIC implements a low-latency and low-overhead line code and is fabricated with a commercial 0.25-µm Silicon-on-Sapphire CMOS technology. The ASIC operates at 640 MHz with a latency of no greater than 6.25 ns and the overhead of 14.3%. The encoder will be integrated with a serialiser and will be used in the A Toroidal LHC ApparatuS Liquid Argon (LAr) calorimeter Phase-I trigger upgrade.

AB - In this article, an encoder Application Specific Integrated Circuit (ASIC) for high-speed serial data transmission is presented. The ASIC implements a low-latency and low-overhead line code and is fabricated with a commercial 0.25-µm Silicon-on-Sapphire CMOS technology. The ASIC operates at 640 MHz with a latency of no greater than 6.25 ns and the overhead of 14.3%. The encoder will be integrated with a serialiser and will be used in the A Toroidal LHC ApparatuS Liquid Argon (LAr) calorimeter Phase-I trigger upgrade.

KW - digital electronic circuits

KW - Front-end electronics for detector readout

KW - high-speed

KW - low-latency

KW - low-overhead

KW - trigger concepts and systems (hardware and software)

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DO - 10.1080/00207217.2016.1218059

M3 - Article

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SN - 0020-7217

VL - 104

SP - 394

EP - 403

JO - International Journal of Electronics

JF - International Journal of Electronics

IS - 3

ER -

Low-latency and low-overhead encoder ASIC in the ATLAS LAr calorimeter trigger upgrade

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Keywords

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