TY - GEN
T1 - IP Protection in TinyML
AU - Wang, Jinwen
AU - Wu, Yuhao
AU - Liu, Han
AU - Yuan, Bo
AU - Chamberlain, Roger
AU - Zhang, Ning
N1 - Publisher Copyright:
© 2023 IEEE.
PY - 2023
Y1 - 2023
N2 - Tiny machine learning (TinyML) is an essential component of emerging smart microcontrollers (MCUs). However, the protection of the intellectual property (IP) of the model is an increasing concern due to the lack of desktop/server-grade resources on these power-constrained devices. In this paper, we propose STML, a system and algorithm co-design to Secure IP of TinyML on MCUs with ARM TrustZone. Our design jointly optimizes memory utilization and latency while ensuring the security and accuracy of emerging models. We implemented a prototype and benchmarked with 7 models, demonstrating STML reduces 40% of model protection runtime overhead on average.
AB - Tiny machine learning (TinyML) is an essential component of emerging smart microcontrollers (MCUs). However, the protection of the intellectual property (IP) of the model is an increasing concern due to the lack of desktop/server-grade resources on these power-constrained devices. In this paper, we propose STML, a system and algorithm co-design to Secure IP of TinyML on MCUs with ARM TrustZone. Our design jointly optimizes memory utilization and latency while ensuring the security and accuracy of emerging models. We implemented a prototype and benchmarked with 7 models, demonstrating STML reduces 40% of model protection runtime overhead on average.
UR - https://www.scopus.com/pages/publications/85173099799
U2 - 10.1109/DAC56929.2023.10247898
DO - 10.1109/DAC56929.2023.10247898
M3 - Conference contribution
AN - SCOPUS:85173099799
T3 - Proceedings - Design Automation Conference
BT - 2023 60th ACM/IEEE Design Automation Conference, DAC 2023
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 60th ACM/IEEE Design Automation Conference, DAC 2023
Y2 - 9 July 2023 through 13 July 2023
ER -