TY - JOUR
T1 - In-Filter Computing for Designing Ultralight Acoustic Pattern Recognizers
AU - Nair, Abhishek Ramdas
AU - Chakrabartty, Shantanu
AU - Thakur, Chetan Singh
N1 - Publisher Copyright:
© 2014 IEEE.
PY - 2022/4/15
Y1 - 2022/4/15
N2 - We present a novel in-filter computing framework that can be used for designing ultralight acoustic classifiers for use in the smart Internet of Things (IoT). Unlike a conventional acoustic pattern recognizer, where the feature extraction and classification are designed independently, the proposed architecture integrates the convolution and nonlinear filtering operations directly into the kernels of a support vector machine (SVM). The result of this integration is a template-based SVM whose memory and computational footprint (training and inference) is light enough to be implemented on a field-programmable gate array (FPGA)-based IoT platform. While the proposed in-filter computing framework is general enough, in this article, we demonstrate this concept using a cascade of an asymmetric resonator with inner hair cells (CAR-IHCs)-based acoustic feature extraction algorithm. The complete system has been optimized using time-multiplexing and parallel-pipeline techniques for a Xilinx Spartan 7 series FPGA. We show that the system can achieve robust classification performance on benchmark sound recognition tasks using only 1.5k lookup tables (LUTs) and 2.8k flip-flops (FFs), a significant improvement over other approaches.
AB - We present a novel in-filter computing framework that can be used for designing ultralight acoustic classifiers for use in the smart Internet of Things (IoT). Unlike a conventional acoustic pattern recognizer, where the feature extraction and classification are designed independently, the proposed architecture integrates the convolution and nonlinear filtering operations directly into the kernels of a support vector machine (SVM). The result of this integration is a template-based SVM whose memory and computational footprint (training and inference) is light enough to be implemented on a field-programmable gate array (FPGA)-based IoT platform. While the proposed in-filter computing framework is general enough, in this article, we demonstrate this concept using a cascade of an asymmetric resonator with inner hair cells (CAR-IHCs)-based acoustic feature extraction algorithm. The complete system has been optimized using time-multiplexing and parallel-pipeline techniques for a Xilinx Spartan 7 series FPGA. We show that the system can achieve robust classification performance on benchmark sound recognition tasks using only 1.5k lookup tables (LUTs) and 2.8k flip-flops (FFs), a significant improvement over other approaches.
KW - Cochlea
KW - edge computing
KW - field-programmable gate array (FPGA)
KW - Internet of Things (IoT)
KW - neuromorphic
KW - support vector machine (SVM)
UR - http://www.scopus.com/inward/record.url?scp=85114728072&partnerID=8YFLogxK
U2 - 10.1109/JIOT.2021.3109739
DO - 10.1109/JIOT.2021.3109739
M3 - Article
AN - SCOPUS:85114728072
SN - 2327-4662
VL - 9
SP - 6095
EP - 6106
JO - IEEE Internet of Things Journal
JF - IEEE Internet of Things Journal
IS - 8
ER -