TY - GEN
T1 - FPGA demonstration of spiking support vector networks based on growth transform neurons
AU - Mackay, John
AU - Gangopadhyay, Ahana
AU - Chakrabartty, Shantanu
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/9/25
Y1 - 2017/9/25
N2 - Growth transform neuron models provide a neuromorphic approach for implementing well established machine learning algorithms while producing neural and population dynamics similar to what have been observed in biology, for example, spiking, bursting and noise-shaping [1]. In this demonstration, we will show some of these dynamics in real-time using an FPGA based acceleration platform that implements a network of growth transform neurons. The demonstration setup (Fig 1) will consist of a custom printed circuit board (PCB) that will interface to a laptop display for real-time display. The PCB will host a USB module, a Spartan 6 field programmable gate array (FPGA), and a VGA adaptor such that it will be possible to output the VGA signal to an external monitor. The FPGA will implement the spiking support vector machine (SVM) using growth transform neuron models in the same manner as described in the appended paper. The inputs to the FPGA will include the network interconnection (synaptic) matrix and will correspond to a SVM kernel matrix. These parameters can be programmed using a laptop as shown in Fig.1.
AB - Growth transform neuron models provide a neuromorphic approach for implementing well established machine learning algorithms while producing neural and population dynamics similar to what have been observed in biology, for example, spiking, bursting and noise-shaping [1]. In this demonstration, we will show some of these dynamics in real-time using an FPGA based acceleration platform that implements a network of growth transform neurons. The demonstration setup (Fig 1) will consist of a custom printed circuit board (PCB) that will interface to a laptop display for real-time display. The PCB will host a USB module, a Spartan 6 field programmable gate array (FPGA), and a VGA adaptor such that it will be possible to output the VGA signal to an external monitor. The FPGA will implement the spiking support vector machine (SVM) using growth transform neuron models in the same manner as described in the appended paper. The inputs to the FPGA will include the network interconnection (synaptic) matrix and will correspond to a SVM kernel matrix. These parameters can be programmed using a laptop as shown in Fig.1.
UR - http://www.scopus.com/inward/record.url?scp=85032677751&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2017.8050401
DO - 10.1109/ISCAS.2017.8050401
M3 - Conference contribution
AN - SCOPUS:85032677751
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
BT - IEEE International Symposium on Circuits and Systems
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 50th IEEE International Symposium on Circuits and Systems, ISCAS 2017
Y2 - 28 May 2017 through 31 May 2017
ER -