Evaluating the use of pre-simulation in VLSI circuit partitioning

Roger D. Chamberlain, Cheryl D. Henderson

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

10 Scopus citations

Abstract

One of the significant difficulties in partitioning logic circuits for distributed simulation is the lack of a priori knowledge concerning the evaluation frequency of individual circuit elements. A number of researchers have resorted to pre-simulation to estimate these evaluation frequencies. In this paper we empirically investigate the wisdom of relying on presimulation results, and evaluate the degree to which early evaluation frequencies predict later evaluation frequencies. The results show that, for simulations that use random input vectors, pre-simulation has clear merit in predicting circuit element evaluation frequency. This supports the use of pre-simulation as an input to circuit partitioning algorithms.

Original languageEnglish
Title of host publicationProceedings of the 8th Workshop on Parallel and Distributed Simulation, PADS 1994
EditorsRajive Bagrodia, D. K. Arvind, Yi-Bing Jason
PublisherAssociation for Computing Machinery, Inc
Pages139-146
Number of pages8
ISBN (Electronic)1565550277, 9781565550278
DOIs
StatePublished - Aug 1 1994
Event8th Workshop on Parallel and Distributed Simulation, PADS 1994 - Edinburgh, United Kingdom
Duration: Jul 6 1994Jul 8 1994

Publication series

NameProceedings of the 8th Workshop on Parallel and Distributed Simulation, PADS 1994

Conference

Conference8th Workshop on Parallel and Distributed Simulation, PADS 1994
Country/TerritoryUnited Kingdom
CityEdinburgh
Period07/6/9407/8/94

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