TY - GEN
T1 - Continuous-time optimization using sub-threshold current-mode growth transform circuits
AU - Gangopadhyay, Ahana
AU - Chatterjee, Oindrila
AU - Chakrabartty, Shantanu
N1 - Funding Information:
VI. ACKNOWLEDGMENT This work was supported by the National Science Foundation under Grant CSR 1405273.
Funding Information:
This work was supported by the National Science Foundation under Grant CSR 1405273.
Publisher Copyright:
© 2018 IEEE
PY - 2019/1/22
Y1 - 2019/1/22
N2 - Analog circuits have long been used for solving various mathematical optimization problems due to their lower latency when compared to their digital counterparts. This paper presents a novel continuous-time analog optimization circuit based on a growth transform-based fixed-point algorithm. The circuit uses translinear MOSFET elements to implement the multiplication and normalization functions using only 5 transistors, whereas continuous-time updates and recursion are implemented using current mirrors. The circuit does not require any additional components to enforce optimization constraints and naturally converges to a steady-state solution corresponding to a local minimum of an objective function. We show that the proposed circuit is generic enough to encompass a multitude of objective functions simply by changing the external circuitry, and the power dissipation of circuit can be adjusted according to the desired latency. For this paper, we present simulation results for specific forms of quadratic and linear cost functions with tunable coefficients, subject to a normalization constraint, and the results show excellent match to floating-point software simulation results.
AB - Analog circuits have long been used for solving various mathematical optimization problems due to their lower latency when compared to their digital counterparts. This paper presents a novel continuous-time analog optimization circuit based on a growth transform-based fixed-point algorithm. The circuit uses translinear MOSFET elements to implement the multiplication and normalization functions using only 5 transistors, whereas continuous-time updates and recursion are implemented using current mirrors. The circuit does not require any additional components to enforce optimization constraints and naturally converges to a steady-state solution corresponding to a local minimum of an objective function. We show that the proposed circuit is generic enough to encompass a multitude of objective functions simply by changing the external circuitry, and the power dissipation of circuit can be adjusted according to the desired latency. For this paper, we present simulation results for specific forms of quadratic and linear cost functions with tunable coefficients, subject to a normalization constraint, and the results show excellent match to floating-point software simulation results.
KW - Analog optimization
KW - Growth transform
KW - Sub-threshold
KW - Translinear principle
UR - http://www.scopus.com/inward/record.url?scp=85062241392&partnerID=8YFLogxK
U2 - 10.1109/MWSCAS.2018.8624043
DO - 10.1109/MWSCAS.2018.8624043
M3 - Conference contribution
AN - SCOPUS:85062241392
T3 - Midwest Symposium on Circuits and Systems
SP - 246
EP - 249
BT - 2018 IEEE 61st International Midwest Symposium on Circuits and Systems, MWSCAS 2018
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 61st IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2018
Y2 - 5 August 2018 through 8 August 2018
ER -