TY - JOUR
T1 - ARYABHAT
T2 - A Digital-Like Field Programmable Analog Computing Array for Edge AI
AU - Kumar, Pratik
AU - Nandi, Ankita
AU - Saha, Ayan
AU - Teja, Kurupati Sai Pruthvi
AU - Das, Ratul
AU - Chakrabartty, Shantanu
AU - Thakur, Chetan Singh
N1 - Publisher Copyright:
© 2004-2012 IEEE.
PY - 2024/5/1
Y1 - 2024/5/1
N2 - Recent advances in margin-propagation (MP) based approximate computing have resulted in analog computing circuits that exhibit scaling properties similar to that of digital computing circuits. MP-based circuits allow trading off energy-efficiency with speed and precision, endow robustness to temperature variations, and make the design portable across different process nodes. In this work, We leverage these scaling properties to design ARYABHAT, a field-programmable analog machine learning processor that can be synthesized like digital field-programmable gate arrays (FPGAs). ARYABHAT features a fully reconfigurable tile-based modular analog architecture with adjustable throughput and configurable energy requirements, making it suitable for various machine-learning computations. The architecture can perform computations at variable accuracy and different power-performance specifications and can simultaneously leverage near-memory computing paradigms to improve computational throughput. We also present a complete programming and test ecosystem for ARYABHAT called ARYAFlow and ARYATest. As proof of concept, we showcase the implementation of machine learning algorithms at different performance specifications.
AB - Recent advances in margin-propagation (MP) based approximate computing have resulted in analog computing circuits that exhibit scaling properties similar to that of digital computing circuits. MP-based circuits allow trading off energy-efficiency with speed and precision, endow robustness to temperature variations, and make the design portable across different process nodes. In this work, We leverage these scaling properties to design ARYABHAT, a field-programmable analog machine learning processor that can be synthesized like digital field-programmable gate arrays (FPGAs). ARYABHAT features a fully reconfigurable tile-based modular analog architecture with adjustable throughput and configurable energy requirements, making it suitable for various machine-learning computations. The architecture can perform computations at variable accuracy and different power-performance specifications and can simultaneously leverage near-memory computing paradigms to improve computational throughput. We also present a complete programming and test ecosystem for ARYABHAT called ARYAFlow and ARYATest. As proof of concept, we showcase the implementation of machine learning algorithms at different performance specifications.
KW - Analog machine learning
KW - analog accelerator
KW - field programmable
KW - margin propagation
KW - neural array
UR - http://www.scopus.com/inward/record.url?scp=85182925037&partnerID=8YFLogxK
U2 - 10.1109/TCSI.2024.3349776
DO - 10.1109/TCSI.2024.3349776
M3 - Article
AN - SCOPUS:85182925037
SN - 1549-8328
VL - 71
SP - 2252
EP - 2265
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
IS - 5
ER -