An energy-scalable margin propagation-based analog VLSI support vector machine

This paper presents a novel approach for designing energy-scalable analog VLSI recognizers. Unlike conventional designs that rely on the translinear response of MOS transistors biased in weak inversion, the proposed approach uses margin propagation, enabling system operation independent of MOS transistor biasing conditions. In this paper margin propagation has been used for designing energy-scalable support vector machines (SVM) whose power and speed requirements can be configured dynamically without any degradation in performance. A prototype SVM operating with 14 dimensional feature vectors and 28 support vectors has been designed and fabricated in a 0.5μm CMOS process. The chip integrates an array of floating gate transistors that serve as storage for SVM parameters. Circuit level simulations demonstrate near identical performance to an equivalent software-based SVM with power dissipation less than 1μW at a rate of 100 classifications per second.