A temperature compensated array of CMOS floating-gate analog memory

Chenling Huang, Shantanu Chakrabartty

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

Floating-gate transistors have been extensively used as analog memory elements in adaptive learning and neural systems. However, conventional techniques for storing and programming sub-threshold currents on floating-gate transistors are sensitive to temperature variations thus limiting their applicability to controlled environments. In this paper, we propose a temperature compensated floating-gate array which can be used to store and program currents down to nanoampere level. The core of the proposed current memory is a dual-channel floating-gate transistor based current reference circuit which uses a linear resistor in translinear loop. As a result the stored current is linearly proportional to the charge on the floating-gate and hence can be precisely programmed. The paper presents results from a prototype fabricated in a 0.5-μm CMOS process which validates the functionality of the proposed current memory cell.

Original languageEnglish
Title of host publicationISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems
Subtitle of host publicationNano-Bio Circuit Fabrics and Systems
Pages109-112
Number of pages4
DOIs
StatePublished - 2010
Event2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 - Paris, France
Duration: May 30 2010Jun 2 2010

Publication series

NameISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems

Conference

Conference2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010
Country/TerritoryFrance
CityParis
Period05/30/1006/2/10

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