A hybrid algorithmic-ΣΔ ADC has been developed for sensor applications that benefit from dynamic reconfiguration of the tradeoff between resolution and conversion speed. By iteratively feeding back and resampling the residue of a ΣΔ conversion, bit weight information is embedded into the digital output sequence as in an algorithmic conversion. By varying the number of sampling and feedback cycles, the ADC can be dynamically reconfigured at the architectural level to be more ΣΔ-like, achieving higher resolution with lower speed, or more algorithmic-like, providing higher speed with lower resolution. With a nominal 10MHz clock, the ADC can resolve 8 bits in 1.6μsec, 16 bits in 51.2μsec or various configurations in between. Analysis of an example sensor application shows a 78% power savings due to dynamic reconfiguration to match signal characteristics.