TY - GEN
T1 - A continuous-time varactor-based temperature compensation circuit for floating-gate multipliers and inner-product circuits
AU - Zhou, Liang
AU - Chakrabartty, Shantanu
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2015/7/27
Y1 - 2015/7/27
N2 - Floating-gate (FG) transistors are commonly used in synthetic neural systems for implementing analog multipliers. However, conventional floating-gate multipliers are sensitive to variations in temperature which limit their application to only controlled environments. Previously, we had reported an off-chip temperature compensation algorithm for floating-gate current memories which used varactors to cancel out the temperature dependent factors. In this paper, we report a continuous-time circuit implementation of the temperature compensation algorithm and show that it enables on-chip implementation of temperature compensated current amplifiers and analog multipliers. Using measured results from fabricated prototypes in a 0.5μm CMOS process, we demonstrate the functionality of the compensation circuit and show that it leads to an order-of-magnitude lower temperature sensitivity for FG multipliers when compared to an uncompensated case.
AB - Floating-gate (FG) transistors are commonly used in synthetic neural systems for implementing analog multipliers. However, conventional floating-gate multipliers are sensitive to variations in temperature which limit their application to only controlled environments. Previously, we had reported an off-chip temperature compensation algorithm for floating-gate current memories which used varactors to cancel out the temperature dependent factors. In this paper, we report a continuous-time circuit implementation of the temperature compensation algorithm and show that it enables on-chip implementation of temperature compensated current amplifiers and analog multipliers. Using measured results from fabricated prototypes in a 0.5μm CMOS process, we demonstrate the functionality of the compensation circuit and show that it leads to an order-of-magnitude lower temperature sensitivity for FG multipliers when compared to an uncompensated case.
UR - http://www.scopus.com/inward/record.url?scp=84946204982&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2015.7169196
DO - 10.1109/ISCAS.2015.7169196
M3 - Conference contribution
AN - SCOPUS:84946204982
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 2513
EP - 2516
BT - 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - IEEE International Symposium on Circuits and Systems, ISCAS 2015
Y2 - 24 May 2015 through 27 May 2015
ER -