Bias-scalability in analog CMOS circuits refers to a current-mode design paradigm where the operation of the circuit remains invariant to the operating conditions (weak-inversion, moderate-inversion or strong-inversion) of the transistors. In this paper we present the design and implementation of a bias-scalable analog support vector machine (SVM) based on our previously reported margin propagation (MP) technique. All the computation in the proposed SVM occur in the logarithmic domain and requires only the use of addition, subtraction and threshold operation which can be implemented using KCL and diodes. The SVM parameters are stored on an array of temperature compensated floating-gate current memories and the training of the SVM is achieved using an offline procedure. Measured results from a SVM prototyped in a 0.5μm CMOS process validates the bias-scalability across different MOSFET operating regimes.