A 7-transistor-per-cell, high-density analog storage array with 500μV update accuracy and greater than 60dB linearity

While floating-gate transistors are attractive as a compact non-volatile storage of analog and neural network parameters, precise and fast adaptation of the stored parameters through digital command and control is a challenge. In this paper we present the design of a high-density array of analog floating-gate memory that can be precisely and independently updated using digital timing interrupts. At the core of the proposed array is our previously reported negative-feedback architecture that allows linearizing of the impact ionized hot-electron injection (IHEI) process and the Fowler-Nordheim (FN) tunneling process in FG transistors. Using a capacitive switching approach, FN tunneling can be independently applied to each of memory cell of the proposed array without affecting the stored values in the other cells. As a result, bi-directional digital updates with accuracy greater than 500μV can be achieved with a linearity of more than 60dB. We have validated the functionality of the analog array using a prototype fabricated in a 0.5μm CMOS process.