TY - JOUR
T1 - A 100 pJ/bit, (32,8) CMOS analog low-density parity-check decoder based on margin propagation
AU - Gu, Ming
AU - Chakrabartty, Shantanu
N1 - Funding Information:
Manuscript received January 04, 2011; revised March 03, 2011; accepted March 14, 2011. Date of publication May 02, 2011; date of current version May 25, 2011. This paper was approved by Associate Editor Stefan Rusu. This work was supported by a research grant from the U.S. National Science Foundation (CCF:0728996).
PY - 2011/6
Y1 - 2011/6
N2 - One of the key factors underlying the popularity of low-density parity-check (LDPC) code is its iterative decoding algorithm which is amenable to efficient analog and digital implementation. However, different applications of LDPC codes (e.g. wireless sensor networks) impose different sets of constraints which include speed, bit error rates (BER) and energy efficiency. Our previous work reported an algorithmic framework for designing margin propagation (MP) based LDPC decoders where the BER performance can be traded off with its energy efficiency. In this paper we present an analog current-mode implementation of an MP-based (32,8) LDPC decoder. The implementation uses only addition, subtraction and threshold operations and hence is independent of transistor biasing. Measured results from prototypes fabricated in a 0.5 μm CMOS process verify the functionality of a (32,8) LDPC decoder and demonstrate the trade-off capability which is realized by adapting a system hyper-parameter. When configured as a min-sum LDPC decoder, the proposed implementation demonstrates superior BER performance compared to the state-of-the-art analog min-sum decoder at SNR greater than 3.5 dB. We show that an optimal configuration of the same MP-based decoder can also deliver up to 3 dB improvement in BER compared to the benchmark min-sum LDPC decoder.
AB - One of the key factors underlying the popularity of low-density parity-check (LDPC) code is its iterative decoding algorithm which is amenable to efficient analog and digital implementation. However, different applications of LDPC codes (e.g. wireless sensor networks) impose different sets of constraints which include speed, bit error rates (BER) and energy efficiency. Our previous work reported an algorithmic framework for designing margin propagation (MP) based LDPC decoders where the BER performance can be traded off with its energy efficiency. In this paper we present an analog current-mode implementation of an MP-based (32,8) LDPC decoder. The implementation uses only addition, subtraction and threshold operations and hence is independent of transistor biasing. Measured results from prototypes fabricated in a 0.5 μm CMOS process verify the functionality of a (32,8) LDPC decoder and demonstrate the trade-off capability which is realized by adapting a system hyper-parameter. When configured as a min-sum LDPC decoder, the proposed implementation demonstrates superior BER performance compared to the state-of-the-art analog min-sum decoder at SNR greater than 3.5 dB. We show that an optimal configuration of the same MP-based decoder can also deliver up to 3 dB improvement in BER compared to the benchmark min-sum LDPC decoder.
KW - Analog decoders
KW - current-mode circuits
KW - error-correcting code
KW - low-density parity-check (LDPC) decoder
KW - margin propagation (MP)
KW - piecewise-linear (PWL) approximation
UR - http://www.scopus.com/inward/record.url?scp=79957661523&partnerID=8YFLogxK
U2 - 10.1109/JSSC.2011.2134550
DO - 10.1109/JSSC.2011.2134550
M3 - Article
AN - SCOPUS:79957661523
SN - 0018-9200
VL - 46
SP - 1433
EP - 1442
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
IS - 6
M1 - 5759722
ER -