A 100 pJ/bit, (32,8) CMOS analog low-density parity-check decoder based on margin propagation

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Abstract

One of the key factors underlying the popularity of low-density parity-check (LDPC) code is its iterative decoding algorithm which is amenable to efficient analog and digital implementation. However, different applications of LDPC codes (e.g. wireless sensor networks) impose different sets of constraints which include speed, bit error rates (BER) and energy efficiency. Our previous work reported an algorithmic framework for designing margin propagation (MP) based LDPC decoders where the BER performance can be traded off with its energy efficiency. In this paper we present an analog current-mode implementation of an MP-based (32,8) LDPC decoder. The implementation uses only addition, subtraction and threshold operations and hence is independent of transistor biasing. Measured results from prototypes fabricated in a 0.5 μm CMOS process verify the functionality of a (32,8) LDPC decoder and demonstrate the trade-off capability which is realized by adapting a system hyper-parameter. When configured as a min-sum LDPC decoder, the proposed implementation demonstrates superior BER performance compared to the state-of-the-art analog min-sum decoder at SNR greater than 3.5 dB. We show that an optimal configuration of the same MP-based decoder can also deliver up to 3 dB improvement in BER compared to the benchmark min-sum LDPC decoder.

Original languageEnglish
Article number5759722
Pages (from-to)1433-1442
Number of pages10
JournalIEEE Journal of Solid-State Circuits
Volume46
Issue number6
DOIs
StatePublished - Jun 2011

Keywords

  • Analog decoders
  • current-mode circuits
  • error-correcting code
  • low-density parity-check (LDPC) decoder
  • margin propagation (MP)
  • piecewise-linear (PWL) approximation

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