TY - JOUR
T1 - A 10-Gb/s Driver/Receiver ASIC and Optical Modules for Particle Physics Experiments
AU - Huang, Xing
AU - Gong, Datao
AU - Hou, Suen
AU - Huang, Guangming
AU - Liu, Chonghan
AU - Liu, Tiankuan
AU - Qi, Ming
AU - Sun, Hanhan
AU - Sun, Quan
AU - Zhang, Li
AU - Zhang, Wei
AU - Zhao, Xiandong
AU - Ye, Jingbo
N1 - Publisher Copyright:
© 1963-2012 IEEE.
PY - 2021/8
Y1 - 2021/8
N2 - We present the design and test results of a Drivers and Limiting AmplifierS ASIC operating at 10 Gb/s (DLAS10) and three miniature optical transmitter/ receiver/transceiver modules (MTx+, MRx+, and MTRx+) based on DLAS10. DLAS10 can drive two transmitter optical subassemblies (TOSAs) of vertical cavity surface emitting lasers (VCSELs), receive the signals from two receiver optical subassemblies (ROSAs) that have no embedded limiting amplifiers (LAs), or drive a VCSEL TOSA and receive the signal from a ROSA, respectively. Each channel of DLAS10 consists of an input continuous time linear equalizer (CTLE), a four-stage LA, and an output driver. The LA amplifies the signals of variable levels to a saturation amplitude of 800 mV (peak-peak). The output driver drives VCSELs or impedance-controlled traces. DLAS10 is fabricated in a 65-nm CMOS technology. The die is 1 mm \times1 mm. DLAS10 is packaged in a 4 mm \times 4 mm 24-pin quad-flat no-leads (QFNs) package. DLAS10 has been tested in MTx+, MRx+, and MTRx+ modules. Both measured optical and electrical eye diagrams pass the 10-Gb/s eye mask test. The input electrical sensitivity is 40 mVp-p, while the input optical sensitivity is -12 dBm. The total jitter of MRx+ is 29 ps (P-P) with a random jitter of 1.6 ps (rms) and a deterministic jitter of 9.9 ps. Each MTx+/MRx+ module consumes 82.6 and 174.4 mW/ch, respectively.
AB - We present the design and test results of a Drivers and Limiting AmplifierS ASIC operating at 10 Gb/s (DLAS10) and three miniature optical transmitter/ receiver/transceiver modules (MTx+, MRx+, and MTRx+) based on DLAS10. DLAS10 can drive two transmitter optical subassemblies (TOSAs) of vertical cavity surface emitting lasers (VCSELs), receive the signals from two receiver optical subassemblies (ROSAs) that have no embedded limiting amplifiers (LAs), or drive a VCSEL TOSA and receive the signal from a ROSA, respectively. Each channel of DLAS10 consists of an input continuous time linear equalizer (CTLE), a four-stage LA, and an output driver. The LA amplifies the signals of variable levels to a saturation amplitude of 800 mV (peak-peak). The output driver drives VCSELs or impedance-controlled traces. DLAS10 is fabricated in a 65-nm CMOS technology. The die is 1 mm \times1 mm. DLAS10 is packaged in a 4 mm \times 4 mm 24-pin quad-flat no-leads (QFNs) package. DLAS10 has been tested in MTx+, MRx+, and MTRx+ modules. Both measured optical and electrical eye diagrams pass the 10-Gb/s eye mask test. The input electrical sensitivity is 40 mVp-p, while the input optical sensitivity is -12 dBm. The total jitter of MRx+ is 29 ps (P-P) with a random jitter of 1.6 ps (rms) and a deterministic jitter of 9.9 ps. Each MTx+/MRx+ module consumes 82.6 and 174.4 mW/ch, respectively.
KW - Analog integrated circuits
KW - high energy physics instrumentation
KW - optical transceivers
UR - http://www.scopus.com/inward/record.url?scp=85107383255&partnerID=8YFLogxK
U2 - 10.1109/TNS.2021.3086481
DO - 10.1109/TNS.2021.3086481
M3 - Article
AN - SCOPUS:85107383255
SN - 0018-9499
VL - 68
SP - 1998
EP - 2004
JO - IEEE Transactions on Nuclear Science
JF - IEEE Transactions on Nuclear Science
IS - 8
M1 - 9447018
ER -