12.3 A Scalable and Instantaneously Wideband 5GS/s RF Correlator Based on Charge Thresholding Achieving 8-bit ENOB and 152 TOPS/W Compute Efficiency

Kareem Rashed, Aswin Undavalli, Shantanu Chakrabartty, Aravind Nagulu, Arun Natarajan

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Correlators are fundamental building blocks in radar/communication signal processing and analog-to-information (A-to-I) applications such as spectrum sensing [1]. Typically, correlation, which is equivalent to an inner (dot) product, is performed using digital multiply-and-accumulate (MAC) operations (Fig. 12.3.1), with power consumption scaling with frequency, compute, and ADC power. Analog correlators eliminate ADCs but suffer from high power/area and/or small correlation lengths (10 samples) [2], [3]. While matrix multiplication in compute-in-memory (CiM) cores can be used for correlation, such blocks typically operate with lower speeds for multi-bit inputs, require new materials/memory IP and DACs and ADCs at the input/output [4], [5].

Original languageEnglish
Title of host publication2024 IEEE International Solid-State Circuits Conference, ISSCC 2024
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages222-224
Number of pages3
ISBN (Electronic)9798350306200
DOIs
StatePublished - 2024
Event2024 IEEE International Solid-State Circuits Conference, ISSCC 2024 - San Francisco, United States
Duration: Feb 18 2024Feb 22 2024

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN (Print)0193-6530

Conference

Conference2024 IEEE International Solid-State Circuits Conference, ISSCC 2024
Country/TerritoryUnited States
CitySan Francisco
Period02/18/2402/22/24

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